`timescale 1ns/1ns
module HDB3_decoder_tb (
    
);


reg clk,rst_n;
wire in;
wire [1:0] HDB3code;
reg [31:0] data;
wire out;

initial begin
    clk = 0;
    rst_n = 1;
    #5 rst_n = 0;
    #10 rst_n = 1;
end

always #5 clk = ~clk;

initial begin
    // data = 32'b0000_1000_0100_0011_0000_1000_0000_0011;
    data = 32'b0000_1000_0011_0100_0000_0001_0000_1000;
end

always @(negedge clk) begin
    #3 data =  {data[30:0],1'b1};
end
assign in = data[31];

HDB3_encoder HDB3_encoder_tb(
.clk(clk),
.rst_n(rst_n),
.code_in(in),
.code_out(HDB3code)

);

HDB3_decoder HDB3_decoder_tb(
.clk(clk),
.rst_n(rst_n),
.in(HDB3code),
.out(out)
);


endmodule //HDB3_decoder_tb